Packaged die on PCB with heat sink encapsulant and methods

ABSTRACT

An apparatus and a method for providing a heat sink on an upper surface of a semiconductor chip by placing a heat-dissipating material thereon which forms a portion of a glob top. The apparatus comprises a semiconductor chip attached to and in electrical communication with a substrate. A barrier glob top material is applied to the edges of the semiconductor chip on the surface (“opposing surface”) opposite the surface attached to the substrate to form a wall around a periphery of the opposing surface of the semiconductor chip wherein the barrier glob top material also extends to contact and adhere to the substrate. The wall around the periphery of the opposing surface of the semiconductor chip forms a recess. A heat-dissipating glob top material is disposed within the recess to contact the opposing surface of the semiconductor chip.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 11/053,082,filed Feb. 7, 2005, pending, which is a continuation of application Ser.No. 10/639,349, filed Aug. 12, 2003, now U.S. Pat. No. 6,853,069, issuedFeb. 8, 2005, which is a continuation of application Ser. No.10/232,782, filed Aug. 28, 2002, now U.S. Pat. No. 6,617,684, issuedSep. 9, 2003, which is a continuation of application Ser. No.09/835,541, filed Apr. 16, 2001, now U.S. Pat. No. 6,534,858, issuedMar. 18, 2003, which is a continuation of application Ser. No.09/189,102, filed Nov. 9, 1998, now U.S. Pat. No. 6,252,308, issued Jun.26, 2001, which is a continuation of application Ser. No. 08/653,030,filed May 24, 1996, now U.S. Pat. No. 5,866,953, issued on Feb. 2, 1999.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an apparatus and a method for providinga heat sink on a semiconductor chip. More particularly, the presentinvention relates to forming a heat sink on an upper surface of asemiconductor chip by placing a heat conductive material thereon whichforms a portion of a glob top.

2. State of the Art

Chip On Board (“COB”) techniques are used to attach semiconductor diceto a printed circuit board including flip chip attachment, wire bondingand tape automated bonding (“TAB”).

Flip chip attachment consists of attaching a flip chip to a printedcircuit board or other substrate. A flip chip is a semiconductor chipthat has a pattern or array of terminations spaced around an activesurface of the flip chip for face-down mounting of the flip chip to asubstrate. Generally the flip chip active surface has one of thefollowing electrical connectors: Ball Grid Array (“BGA”), wherein anarray of minute solder balls is disposed on the surface of a flip chipwhich attaches to the substrate (“the attachment surface”); SlightlyLarger than Integrated Circuit Carrier (“SLICC”), which is similar to aBGA but has a smaller solder ball pitch and diameter than a BGA; or aPin Grid Array (“PGA”), wherein an array of small pins extendssubstantially perpendicularly from the attachment surface of a flip chipwherein the pins conform to a specific arrangement on a printed circuitboard or other substrate for attachment thereto. With the BGA or SLICC,the solder or other conductive ball arrangement on the flip chip must bea mirror image of the connecting bond pads on the printed circuit boardsuch that precise connection is made. The flip chip is bonded to theprinted circuit board by reflowing the solder balls. The solder ballsmay also be replaced with a conductive polymer. With the PGA, the pinarrangement of the flip chip must be a mirror image of the pin recesseson the printed circuit board. After insertion, the flip chip isgenerally bonded by soldering the pins into place. An underfillencapsulant is generally disposed between the flip chip and the printedcircuit board for environmental protection and to enhance the attachmentof the flip chip to the printed circuit board. A variation of thepin-in-recess PGA is a J-lead PGA wherein the loops of the J's aresoldered to pads on the surface of the circuit board.

Wire bonding and TAB attachment generally begin with attaching asemiconductor chip to the surface of a printed circuit board with anappropriate adhesive such as an epoxy. In wire bonding, a plurality ofbond wires is attached one at a time to each bond pad on thesemiconductor chip and extends to a corresponding lead or trace end onthe printed circuit board. The bond wires are generally attached throughone of three industry-standard wire bonding techniques: ultrasonicbonding, using a combination of pressure and ultrasonic vibration burststo form a metallurgical cold weld; thermocompression bonding, using acombination of pressure and elevated temperature to form a weld; andthermosonic bonding, using a combination of pressure, elevatedtemperature and ultrasonic vibration bursts. The semiconductor chip maybe oriented either face up or face down (with its active surface andbond pads either up or down with respect to the circuit board) for wirebonding, although face up orientation is more common. With TAB, ends ofmetal leads carried on an insulating tape such as a polyamide arerespectively attached to the bond pads on the semiconductor chip and tothe lead or trace ends on the printed circuit board. An encapsulant isgenerally used to cover the bond wires and metal tape leads to preventcontamination.

After assembly as shown in FIG. 1, a glob of encapsulant material 102(usually epoxy or silicone or a combination thereof) is generallyapplied to a COB assembly 100 to surround a semiconductor chip or flipchip 104 which is attached to a substrate 106 via a plurality ofelectrical connections 108 which extends between a plurality ofsemiconductor chip bond pads 110 and a corresponding plurality ofsubstrate bond pads 112. An underfill encapsulant 114 is dispensedbetween the semiconductor chip 104 and the substrate 106. As shown inFIG. 2, the glob top materials 202 are often used to hermetically sealbare dice 204 (shown in shadow) on a printed circuit board 206 such asSIMM modules to form a COB assembly 200. The organic resins generallyused in the glob top encapsulation are usually selected for low moisturepermeability and low thermal coefficient of expansion to avoid exposureof the encapsulated chip to moisture or mechanical stress respectively.However, even though the chemical properties of these glob top materialshave desirable properties for encapsulation, the thermal and electricalproperties are often not optimal for removing heat efficiently away fromthe semiconductor dice or for use in high temperature areas.

Every semiconductor chip in a COB assembly generates some heat duringoperation. Some glob tops and package encapsulation materials serve todraw the heat away from most semiconductor chips. Indeed, one factor inchoosing a package encapsulation material is its thermal dissipationproperties. If the temperature of the semiconductor chip is notcontrolled or accommodated, system reliability problems may occur due toexcess temperature rise during operation. The device/semiconductorjunction temperature (the location of the heat source due to powerdissipation) must be maintained below a limiting value such as 85° C.The primary reason to control this temperature is that switching voltageis a sensitive function of device temperature. In addition, variousfailure mechanisms are thermally activated and failure rates becomeexcessive above the desired temperature limit. Furthermore, it isimportant to control the variation in device operating temperatureacross all the devices in the system. This is also due to thetemperature sensitivity of switching voltage since too large a variationfrom device to device would increase the voltage range over whichswitching occurs, leading to switching errors due to noise andpower-supply fluctuations. Moreover, the fluctuations in temperaturecause differential thermal expansions which give rise to a fatigueprocess that can lead to cracks occurring in the COB assembly duringburn-in or general operation.

Thus high heat-producing semiconductor dice such as microprocessors mayrequire adjustments in the size of the COB assembly and will oftenrequire the addition of metal heat-dissipating fins, blocks or the likeon the package. FIG. 3 illustrates a finned COB assembly 300. The finnedCOB assembly 300 comprises a semiconductor chip or flip chip 302 whichis attached to a substrate 304 via a plurality of electrical connections306 which extends between a plurality of semiconductor chip bond pads308 and a corresponding plurality of substrate bond pads 310. Anunderfill encapsulant 312 is dispensed between the semiconductor chip302 and the substrate 304. A cap 314 having a plurality ofheat-dissipating fins 316 is attached to an upper surface 318 of thesemiconductor chip 302 with a layer of thermally conductive adhesive320. The addition of heat-dissipating fins, blocks or the likesubstantially increases the cost of production for COB assemblies.

Other means for heat dissipation have also been attempted. U.S. Pat. No.5,434,105 issued Jul. 18, 1995, to Liou relates to the use of heatspreaders attached to a semiconductor device by a glob top to strengthenthe heat coupling from an integrated circuit die to the lead framewherein heat can then pass through the leads of the lead frame to thecircuit board. However, the heat is not dissipated away from thecircuit. Rather, the heat is conducted into the circuit board, which canstill cause heat related problems. U.S. Pat. No. 5,488,254 issued Jan.30, 1996, to Nishimura et al. and U.S. Pat. No. 5,489,801 issued Feb. 6,1996, to Blish relate to encasing a heat slug (a piece of heatconducting material) in the encapsulation material. Although each ofthese patents attempts to address the problems of potential differencesin the thermal coefficient of expansion between the heat slug and theencapsulation material, these attempts are never entirely successful andthe adhesion interfaces between the heat slug and the encapsulationmaterial may become separated, allowing moisture to reach and destroythe encased chip.

Changes in encapsulation materials have also been attempted to achievehigh thermal conductivity, low coefficient of thermal expansion and lowmoisture permeability. U.S. Pat. No. 4,358,552 issued Nov. 9, 1982, toShinohara et al. and U.S. Pat. No. 4,931,852 issued Jun. 5, 1990, toBrown et al. are examples of such attempts. However, no attempt has beenentirely successful in balancing all of these desired factors or aresimply too expensive.

U.S. Pat. No. 5,379,186 issued Jan. 3, 1995, to Gold et al. (“Gold”)relates to a heat-producing semiconductor chip attached to a substratewhich uses multiple encapsulants to dissipate heat. “Gold” teachesplacing a layer of encapsulant material over the semiconductor chip witha layer of thermally conductive material applied over the encapsulantmaterial layer. “Gold” specifically teaches that the encapsulantmaterial layer used for covering the semiconductor is a relatively poorconductor of heat (i.e., an insulative material) which is assumedlychosen for its adherence and protective properties. The thermallyconductive material is applied over the encapsulant material to aid inthe removal of heat from the semiconductor device through the insulatingencapsulant material. However, this invention is inherently inefficientsince the heat must be drawn from an insulative material.

Therefore, it would be advantageous to develop a technique and assemblyfor inexpensively forming a heat-dissipating mechanism on asemiconductor chip in combination with commercially available, widelypracticed semiconductor device fabrication techniques.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to an apparatus and a method for providinga heat sink on a semiconductor chip. The apparatus is constructed with atwo-step process for forming a dual material glob top. The processcomprises providing a semiconductor chip attached to and in electricalcommunication with a substrate by any known industry technique such asflip chip attachment, TAB attachment, wire bonding and the like. Abarrier glob top material is applied to the edges of the semiconductorchip on the surface (“opposing surface”) opposite the surface(“attachment surface”) attached to the substrate to form a wall around aperiphery of the opposing surface of the semiconductor chip and extendsto contact and adhere to the substrate. The barrier glob top performsthe function of sealing and protecting the semiconductor chip. Thus thebarrier glob top material is selected for low moisture permeability, lowthermal coefficient of expansion, and good adhesion and sealingproperties. Preferred barrier glob top materials include epoxy,polyamide, urethane silicone, acrylic or the like.

If the semiconductor chip makes electrical contact between the opposingside and the substrate with bond wires or TAB, the wall formed aroundthe periphery of the opposing surface preferably covers and encapsulatesthe bond wires or TAB. If the semiconductor chip is a flip chip, anunderfill encapsulant may be disposed between the semiconductor chip andthe substrate.

The wall around the periphery of the opposing surface of thesemiconductor chip forms a recess. A heat-dissipating glob top materialis disposed within the recess to contact the opposing surface of thesemiconductor chip. The heat-dissipating glob top material is chosen forits ability to transfer heat away from the semiconductor chip (i.e.,high thermal conductivity material). As a general matter, theheat-dissipating glob top material has a higher thermal conductivitythan the barrier glob top material. The heat-dissipating glob top mayalso extend over the barrier glob top wall to contact the substrate. Itis also understood that a plurality of semiconductor chips with barrierglob tops could be attached to a substrate with a continuousheat-dissipating glob top filling each semiconductor chip barrier globtop recess and covering each of the plurality of semiconductor chips.Preferred heat-dissipating glob top materials include: standard, highpurity barrier glob top materials containing arsenic, boron, gallium,germanium, phosphorus, silicon or other such suitable highly conductivematerials.

Differences in the thermal coefficient of expansion between the barrierglob top and the heat-dissipating glob top and the potential ofseparation of the interface between the barrier glob top and theheat-dissipating glob top are less an issue with the present inventionsince the barrier glob top completely seals the semiconductor chip frommoisture or external contamination.

Thus, the apparatus of the present invention has all of the adherenceand sealing benefits of a low thermal conductivity glob top materialwhile at the same time enjoying the benefits of heat-dissipationprovided by a high thermal conductivity glob top material.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming that which is regarded as the present invention,the advantages of this invention can be more readily ascertained fromthe following description of the invention when read in conjunction withthe accompanying drawings in which:

FIG. 1 is a side cross-sectional view of a prior art glob topencapsulated semiconductor chip attached to a substrate;

FIG. 2 is an oblique plan view of a prior art substrate with a pluralityof semiconductors attached to a substrate with a glob top encapsulation;

FIG. 3 is a side cross-sectional view of a prior art semiconductorassembly with heat-dissipating fins attached to a substrate;

FIG. 4 is a side cross-sectional view of a first encapsulatedsemiconductor assembly of the present invention;

FIG. 5 is an oblique plan view of the first encapsulated semiconductorassembly of FIG. 4;

FIG. 6 is a side cross-sectional view of a second encapsulatedsemiconductor assembly of the present invention;

FIG. 7 is a side cross-sectional view of a third encapsulatedsemiconductor assembly of the present invention;

FIG. 8 is a side cross-sectional view of a fourth encapsulatedsemiconductor assembly of the present invention; and

FIG. 9 is a side cross-sectional view of a multiple encapsulatedsemiconductor dice assembly of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 4 illustrates a first encapsulated semiconductor assembly 400 ofthe present invention. The first encapsulated semiconductor assembly 400comprises a flip chip or semiconductor chip 402 having a plurality ofbond pads 404 on an active surface 406 of the semiconductor chip 402. Afacing surface 408 of each bond pad 404 has a conductive pad 410 inelectrical communication therewith. The conductive pads 410 are inelectrical communication with a plurality of respective bond pads 412 onan upper surface 414 of a substrate 416. Each substrate bond pad 412 isconnected on a lower bond pad surface 418 to a trace lead 420 (shown bya dashed line). An underfill encapsulant 422 may be disposed between thesemiconductor chip 402 and the substrate 416.

As seen in FIGS. 4 and 5, a barrier glob top 424 is applied to surrounda periphery of the semiconductor chip 402 which seals and protects thesemiconductor chip 402 and forms a recess or cavity 426. Aheat-dissipating glob top 428 is disposed within the recess 426 as shownin FIG. 4.

FIG. 6 illustrates a second encapsulated semiconductor assembly 600 ofthe present invention. The encapsulated semiconductor assembly 600comprises a semiconductor chip 602 attached by a back side 604 to afacing surface 606 of a substrate 608. The semiconductor chip 602 has aplurality of bond pads 610 on an active surface 612 of the semiconductorchip 602. A facing surface 614 of each bond pad 610 has a bond wire 616in electrical communication therewith. Each bond wire 616 is inelectrical communication with a respective bond pad 620 on the substratefacing surface 606. Each substrate bond pad 620 is connected on a lowerbond pad surface 622 to a trace lead 624 (shown by a dashed line). Abarrier glob top 626 is applied to surround a periphery of thesemiconductor chip 602, forming a recess or cavity 628. Aheat-dissipating glob top 630 is disposed within the recess 628.

FIG. 7 illustrates a third encapsulated semiconductor assembly 700 ofthe present invention. The third encapsulated semiconductor assembly 700is similar to the second encapsulated semiconductor assembly 600;therefore, components common to FIGS. 6 and 7 retain the same numericdesignation. The difference between the third encapsulated semiconductorassembly 700 and the second encapsulated semiconductor assembly 600 isthat the third encapsulated semiconductor assembly 700 has a pluralityof TAB attachments 702 forming an electrical communication between thefacing surface 614 of the semiconductor chip bond pad 610 and thesubstrate bond pads 620 rather than the bond wires 616 of the secondencapsulated semiconductor assembly 600.

FIG. 8 illustrates a fourth encapsulated semiconductor assembly 800 ofthe present invention. The fourth encapsulated semiconductor assembly800 is similar to the second encapsulated semiconductor assembly 600;therefore, components common to FIGS. 6 and 8 retain the same numericdesignation. The difference between the fourth encapsulatedsemiconductor assembly 800 and the second encapsulated semiconductorassembly 600 is that the fourth encapsulated semiconductor assembly 800has a heat-dissipating glob top 802 which is disposed within the recess628 and extends over the barrier glob top 626 to contact and adhere tothe substrate 608.

FIG. 9 illustrates a multiple encapsulated semiconductor dice assembly900 of the present invention. The multiple encapsulated semiconductordice assembly 900 is similar to the fourth encapsulated semiconductorassembly 800; therefore, components common to FIGS. 8 and 9 retain thesame numeric designation. The difference between the multipleencapsulated semiconductor dice assembly 900 and the fourth encapsulatedsemiconductor assembly 800 is that the multiple encapsulatedsemiconductor dice assembly 900 has multiple semiconductor dice 902 and904 with a heat-dissipating glob top 802 which extends over thesemiconductor dice 902 and 904 to contact and adhere to the substrate608.

Having thus described in detail preferred embodiments of the presentinvention, it is to be understood that the invention defined by theappended claims is not to be limited by particular details set forth inthe above description as many apparent variations thereof are possiblewithout departing from the spirit or scope thereof.

1. An assembly method for a semiconductor assembly having a substrateand a semiconductor chip having a first surface and a second surfacecomprising: attaching at least a portion of the first surface of thesemiconductor chip to at least a portion of the substrate; forming anelectrical connection between the semiconductor chip and the substrate;forming a wall substantially around a periphery of the second surface ofthe semiconductor chip using a barrier material, the wall around theperiphery of the second surface of the semiconductor chip defining arecess, the barrier material having a first thermal conductivity;extending the barrier material to contact the substrate; and disposing aheat-dissipating material substantially within the recess, theheat-dissipating material having a second thermal conductivity differentthan the first thermal conductivity of the barrier material.
 2. Themethod of claim 1, wherein the second thermal conductivity of theheat-dissipating material is greater than the first thermal conductivityof the barrier material.
 3. The method of claim 1, wherein theelectrical connection between the semiconductor chip and the substratecomprises attaching at least one bond wire between at least oneelectrical contact point on the second surface of the semiconductor chipand a respective electrical contact point on the substrate.
 4. Themethod of claim 1, wherein the barrier material substantiallyencapsulates the at least one bond wire.
 5. The method of claim 1,wherein the electrical connection between the semiconductor chip and thesubstrate comprises attaching at least one tape automated bond betweenat least one electrical contact point on the second surface of thesemiconductor chip and a respective electrical contact point on thesubstrate.
 6. The method of claim 5, wherein the barrier materialsubstantially encapsulates the at least one tape automated bond.
 7. Themethod of claim 1, wherein the electrical connection between thesemiconductor chip and the substrate comprises attaching at least oneconductive bond between at least one electrical contact point on thesecond surface of the semiconductor chip and a respective electricalcontact point on the substrate.
 8. The method of claim 7, furthercomprising disposing an underfill encapsulant substantially between thesemiconductor chip and the substrate.
 9. A method of making asemiconductor assembly having a substrate and a plurality ofsemiconductor chips, each semiconductor chip of the plurality having afirst surface and a second surface, comprising: attaching a portion ofthe first surface of each semiconductor chip to a portion of thesubstrate; disposing an underfill material substantially between thesubstrate and each semiconductor chip; forming an electrical connectionbetween each semiconductor chip and the substrate; forming a wallsubstantially around a periphery of the second surface of eachsemiconductor chip using a barrier material, the wall and the secondsurface of each semiconductor chip defining a recess, the barriermaterial having a first thermal conductivity; extending the barriermaterial to contact and adhere to the substrate; and disposing aheat-dissipating material substantially within the recess, theheat-dissipating material having a second thermal conductivity differentthan the first thermal conductivity of the barrier material.
 10. Themethod of claim 9, wherein the second thermal conductivity of theheat-dissipating material is greater than the first thermal conductivityof the barrier material.
 11. The method of claim 9, wherein theelectrical connection between each semiconductor chip and the substratecomprises attaching at least one bond wire between at least oneelectrical contact point on the second surface of each semiconductorchip and a respective electrical contact point on the substrate.
 12. Themethod of claim 11, wherein the barrier material substantiallyencapsulates the at least one bond wire.
 13. The method of claim 11,wherein the electrical connection between each semiconductor chip andthe substrate comprises attaching at least one tape automated bondbetween at least one electrical contact point on the second surface ofeach semiconductor chip and a respective electrical contact point on thesubstrate.
 14. The method of claim 13, wherein the barrier materialsubstantially encapsulates the at least one tape automated bond.
 15. Themethod of claim 9, wherein the electrical connection between eachsemiconductor chip and the substrate comprises attaching at least oneconductive bond between at least one electrical contact point on thesecond surface of each semiconductor chip and a respective electricalcontact point on the substrate.
 16. A heat transfer method for asemiconductor assembly having a substrate and a plurality ofsemiconductor chips, each semiconductor chip of the plurality having afirst surface and a second surface, comprising: attaching a portion ofthe first surface of each semiconductor chip to a portion of thesubstrate; disposing an underfill material substantially between thesubstrate and each semiconductor chip; forming an electrical connectionbetween each semiconductor chip and the substrate; forming a wallsubstantially around a periphery of the second surface of eachsemiconductor chip using a barrier material, the wall and the secondsurface of each semiconductor chip defining a recess, the barriermaterial having a first thermal conductivity; extending the barriermaterial to contact and adhere to the substrate; and disposing aheat-dissipating material substantially within the recess, theheat-dissipating material having a second thermal conductivity differentthan the first thermal conductivity of the barrier material.
 17. Themethod of claim 16, wherein the second thermal conductivity of theheat-dissipating material is greater than the first thermal conductivityof the barrier material.
 18. The method of claim 16, wherein theelectrical connection between each semiconductor chip and the substratecomprises attaching at least one bond wire between at least oneelectrical contact point on the second surface of each semiconductorchip and a respective electrical contact point on the substrate.
 19. Themethod of claim 18, wherein the barrier material substantiallyencapsulates the at least one bond wire.
 20. The method of claim 18,wherein the electrical connection between each semiconductor chip andthe substrate comprises attaching at least one tape automated bondbetween at least one electrical contact point on the second surface ofeach semiconductor chip and a respective electrical contact point on thesubstrate.
 21. The method of claim 20, wherein the barrier materialsubstantially encapsulates the at least one tape automated bond.
 22. Themethod of claim 16, wherein the electrical connection between eachsemiconductor chip and the substrate comprises attaching at least oneconductive bond between at least one electrical contact point on thesecond surface of each semiconductor chip and a respective electricalcontact point on the substrate.